A Survey on Efficient Training of Transformers
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Continuum Knowledge
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This survey paper, titled "A Survey on Efficient Training of Transformers," provides a comprehensive overview of the recent progress in accelerating the training of Transformer models, focusing on both computation and memory efficiency.
The authors highlight the importance of developing efficient training techniques to make Transformer training faster, more cost-effective, and more accurate by efficiently using computational and memory resources.
The paper is organized into two main sections: computation efficiency and memory efficiency. Let's summarize each section in detail.
Optimisation
Optimisers: The survey discusses various optimizers, including SGD with momentum, Adam, AdamW, and the recently discovered Lion optimizer. Lion converges faster and is more memory-efficient and accurate than AdamW for training Transformers on various benchmarks.
Initialization: Proper initialization is crucial for stabilizing training, enabling higher learning rates, accelerating convergence, and improving generalization. Techniques like Fixup, ReZero, SkipInit, and T-Fixup are discussed.
Sparse training: The key idea is to directly train sparse subnetworks instead of the full networks from scratch without sacrificing accuracy. Techniques like the lottery ticket hypothesis (LTH) and its variants are discussed.
Overparameterization: Increasing the number of learnable parameters beyond the number of training samples can improve convergence and generalization. The survey discusses theoretical guarantees and practical applications of overparameterization in Transformers.
Large batch training: Using large batch sizes can reduce the number of iterations per epoch and improve computing resource utilization. Techniques like linear scaling of the learning rate, LARS, and LAMB are discussed.
Incremental learning: This approach involves relaxing the original optimization problem into a sequence of easy-to-optimize sub-problems. Techniques like progressive layer stacking, stochastic depth, and AutoProg are discussed.
Parallelism: Various parallelism techniques, such as data parallelism, model parallelism, pipeline parallelism, and tensor parallelism, are discussed to distribute the workload and memory across multiple devices.
Quantized training: Quantization techniques, such as mixed-precision training and integer-only quantization, are discussed to reduce memory consumption and accelerate computation.
Rematerialization: This technique involves recomputing activations during the backward pass instead of storing them in memory, reducing memory consumption at the cost of additional computation.
Offloading: Offloading techniques, such as CPU offloading and NVMe offloading, are discussed to store intermediate activations on slower but larger memory devices.
Parameter-efficient tuning: These methods aim to adapt pretrained models to downstream tasks with fewer trainable parameters, reducing memory consumption and training time. Techniques like adapter tuning, prompt tuning, and LoRA are discussed.
Use state-of-the-art optimizers like Lion for faster convergence and better memory efficiency.
Employ proper initialization techniques like T-Fixup to stabilize training and enable higher learning rates.
Consider sparse training techniques like LTH to reduce the number of trainable parameters without sacrificing accuracy.
Utilize large batch training with techniques like LARS or LAMB to improve computing resource utilization.
Apply parallelism techniques to distribute the workload and memory across multiple devices.
Use quantization techniques like mixed-precision training to reduce memory consumption and accelerate computation.
Employ rematerialization to reduce memory consumption by recomputing activations during the backward pass.
Consider offloading techniques to store intermediate activations on slower but larger memory devices.
Utilize parameter-efficient tuning methods like adapter tuning or LoRA to adapt pretrained models to downstream tasks with fewer trainable parameters.
In conclusion, this survey provides a comprehensive overview of the recent progress in efficient training techniques for Transformers, covering both computation and memory efficiency. By leveraging these techniques, researchers and practitioners can train large-scale Transformer models more efficiently, reducing the computational and memory requirements while maintaining high accuracy.
In this section, the authors discuss data efficiency as another crucial factor in efficient training, focusing on two main approaches: token masking and importance sampling.
Token masking is a widely used technique in self-supervised pre-training tasks, such as masked language modeling (MLM) and masked image modeling (MIM).
The main idea is to randomly mask some input tokens and train the model to predict the missing content (e.g., vocabulary ID or pixels) using the context information from the visible tokens.
Since the computational and memory complexity of Transformer models grows quadratically with the sequence length, removing the masked tokens can significantly improve training efficiency. The authors discuss two examples:
a) In MLM, jointly pre-training the encoder and decoder for language generation tasks while removing the masked tokens in the decoder can save memory and computation costs.
b) In MIM, removing the masked image patches before the encoder has been shown to achieve stronger performance and 3× or more lower overall pre-training time and memory consumption compared to keeping the masked tokens.
The authors also mention that in language-image pre-training, randomly masking and removing the masked image patches can lead to 3.7× faster overall pre-training time compared to the original CLIP approach.
Importance sampling, also known as data pruning, aims to accelerate stochastic gradient algorithms for supervised learning by prioritising informative training examples. This approach is theoretically guaranteed to reduce variance and speed up convergence.
For deep neural networks (DNNs), a common way to estimate per-sample importance is to use gradient norms.
The authors discuss several works that use different approximations to make calculating these norms tractable. One work shows that simple average gradient norms or error 2-norms over several weight initializations can be used to identify important examples at a very early stage in training, similar to the early-bird lottery ticket hypothesis (LTH) but in the data domain.
A more recent work demonstrates an exciting analytic theory showing that the scaling of test error with dataset size can break beyond power scaling laws and be reduced to at least exponential scaling if equipped with a superior data pruning metric.
The authors employ a self-supervised metric using k-means clustering, suggesting a promising direction towards more efficient neural scaling laws based on data importance sampling.
In summary, this section highlights the importance of data efficiency in efficient training of Transformers.
Token masking, by removing masked tokens during pre-training, can significantly reduce computational and memory complexity.
Importance sampling, by prioritising informative training examples based on gradient norms or other metrics, can accelerate convergence and improve generalization.
These techniques complement the model-centric approaches discussed in the other sections of the paper to further improve the efficiency of training large-scale Transformer models.
The "Memory Efficiency" section of the survey discusses various techniques to optimise memory usage when training large Transformer models that do not fit into the memory of a single device.
The authors first analyse the memory consumption of existing model training frameworks, which is primarily occupied by model states (optimizer states, gradients, and parameters) and activations.
The dominant solutions to optimize memory usage are as follows:
Training large DNNs with parallelism across devices is a common practice to meet memory demands.
The two main paradigms are Data Parallelism (DP) and Model Parallelism (MP).
DP distributes a minibatch of data across different devices, while MP allocates subgraphs of a model across multiple workers. DP is suitable for training small to moderate models, but it has poor memory efficiency when models become large. To improve the scalability of DP, solutions like parameter sharing (Albert) and ZeRO have been proposed.
To deal with very large DNNs, MP is used to allocate different layers across multiple accelerators in a "vertical" manner. Although MP has good memory efficiency, its communication and computation efficiency is low. To boost MP efficiency in an orthogonal "horizontal" dimension, two strategies are used: Tensor Parallelism (TP) and Pipeline Parallelism (PP). TP partitions a tensor operation in a layer across workers for faster computation and more memory saving, while PP splits the input mini-batch into multiple smaller micro-batches, enabling different accelerators to work on different micro-batches simultaneously. DP and MP can be used together to train larger models with higher computation and memory capacity.
This technique trains neural networks from scratch in reduced precision by compressing the activations, weights, and gradients into low-bit values (e.g., FP16 or INT8).
The most widely adopted approach for Transformers is automatic mixed-precision (AMP) training, which stores a master copy of weights in full-precision for updates while the activations, gradients, and weights are stored in FP16 for arithmetic.
AMP achieves faster training/inference speed and reduces memory consumption during network training. Recent support for FP8 training on NVIDIA H100 has shown promising results on Transformer training. Activation compressed training (ACT) is another technique that stores low-precision approximate copies of activations while computing the forward pass exactly, helping to reduce overall memory consumption during training.
Rematerialization, also known as checkpointing, is a technique that only stores a portion of activations/weights during the forward pass and recomputes the rest during the backward pass.
Offloading is a technique that uses external memory, such as CPU memory, as an extension of GPU memory to increase memory capacity during training.
The optimal choice needs to minimize communication cost, reduce CPU computation, and maximize GPU memory saving. ZeRO-Offload is a representative work that offers an optimal offloading strategy customized to mixed-precision training with the Adam optimizer.
Parameter-efficient tuning:
This technique is becoming a prevailing way to drastically cut training costs by efficiently tuning readily available pretrained models.
Parameter-efficient tuning (PET) only updates a small number of additional parameters while freezing the pretrained model, significantly reducing the storage burden.
PET approaches can be categorized into addition-based methods and reparameterization-based methods.
The former attaches additional trainable parameters to the pretrained model, while the latter tunes parameters that are inherently in the model or new parameters that can be reparameterized into the model, yielding no sacrifice on inference efficiency. LoRA is a representative work that approximates the update of self-attention weights into two low-rank matrices, which can be merged into the pretrained weights during inference.
This section of the survey discusses the importance of designing efficient hardware accelerators to enable faster training and inference for DNNs, especially Transformers.
The authors highlight the advantages and disadvantages of various hardware platforms, such as CPUs, GPUs, ASICs, and FPGAs, and emphasize the importance of considering hardware constraints and capabilities when designing algorithms.
The main techniques for hardware/algorithm co-design are as follows
Sparse matrix multiplication
Sparse general matrix multiplication (SpGEMM) takes advantage of the sparsity of attention matrices to reduce the number of computations.
Popular sparse matrix computation libraries include Intel Math Kernel Library on CPU and cuSPARSE, CUSP, and 2:4 structured sparsity on GPU.
However, SpGEMM is often hardware-unfriendly to general-purpose processors due to irregular sparsity. Specialized hardware accelerators, such as FPGAs and ASICs, are required to handle the poor data locality issue. OuterSPACE is a custom accelerator that transforms matrix multiplication into an outer product procedure and eliminates redundant memory accesses by decoupling multiplication from accumulation.
ViTCoD uses a learnable auto-encoder to compress sparse attentions and designs encoder and decoder engines to boost hardware utilization.
Lowering the precision of computations reduces the amount of memory and computation, which can be implemented in hardware-friendly fixed-point or integer representations instead of floating-point ones.
This results in a significant improvement in power consumption and speedup.
Low-precision arithmetic can be combined with other techniques, such as pruning and low-rank approximation, to achieve further acceleration. Sanger uses 4-bit queries and keys to compute the quantized prediction of sparse attention matrix and rearranges sparse attention masks into structured blocks for processing by reconfigurable hardware. DOTA identifies unimportant connections in attention using low-rank transformation and low-precision computation, achieving a 152.6× speedup over GPU by incorporating token-level parallelism and out-of-order execution.
Efficient attention
Several pioneering works focus on efficient and lightweight attention implementation in hardware.
A3 selects only those keys that are likely to have high similarity with the given queries to reduce the amount of computation in attention.
ELSA filters out irrelevant keys for a particular query based on hashing similarity to save computation, achieving a speedup of 58.1× and three orders of magnitude improvements in energy efficiency compared to an Nvidia V100 GPU.
FlashAttention proposes to exploit tiling to reduce the I/O communication between GPU high bandwidth memory (HBM) and on-chip SRAM, becoming a default fast and memory-efficient attention module for speedup.
In summary, this section highlights the importance of hardware/algorithm co-design in optimizing the training efficiency of Transformers. By considering the constraints and capabilities of hardware when designing algorithms, researchers can develop techniques such as sparse matrix multiplication, hardware-aware low-precision computation, and efficient attention implementations to significantly improve the speed, power consumption, and energy efficiency of training and inference for Transformers.
Overall, this survey provides a comprehensive overview of the state-of-the-art techniques for efficient training of Transformers, covering computation efficiency, memory efficiency, and hardware/algorithm co-design. The insights and techniques presented in this paper can help researchers and practitioners optimize the training of large-scale Transformer models, making them more accessible and environmentally friendly.
